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Chapter 1
Depending on the base board, the USB interface can be realized either as host1 or
device0, the signals have the following meaning:
Signal
USBP
USBN
USB_DT/PW
USB host1
Differential data+ DP1
Differential data- DN1
USB Power Enable
USB device0
Differential data + PDPO
Differential data- PDNO
USB Detect
Note: The USBP and USBN lines should have 15k pull down resistors to prevent the
module from hanging on bootup. Please see the development board schematic for
more information.
At the module specific pins of the system connector a second host interface (host0) is
provided with the differential data lines DP0 and DN0.
Ethernet interface
The ConnectCore 9M 2443 module has a 10/100Mbit Ethernet controller with
integrated MAC and PHY on board.
Features:
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Embedded 16Kbyte FIFO for packet buffers
Support burst-mode read for highest performance applications
Configurable Interrupt pin with programmable hold-off timer
Compatible with IEEE802.3, 802.3u standards
Integrate Fast Ethernet MAC/PHY transceiver in one chip
10Mbps and 100Mbps data rate
Full and half duplex operations
10/100Mbps Auto-negotiation operation
Twisted pair crossover detection and auto-correction (HP Auto-MDIX)
IEEE 802.3x flow control for full-duplex operation
Back-pressure flow control for half-duplex operation
Wake-on-LAN capabilities:
? Detection of a change in the network link state
? Receipt of a Magic Packet
LED pins for various network activity indications
The Ethernet controller is connected to CS5#. Its programmable polarity interrupt
output is connected to the interrupt input EINT9 of the CPU.
Global signals on the system connector only indicate the Link/Activity-LED is being
used.
35
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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